1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a voltage clamping circuit for a semiconductor memory device adapted to clamp an output voltage from the semiconductor memory device to a desired level in a certain voltage variation interval of an external supply voltage.
2. Description of the Related Art
Semiconductor memory devices include a DC voltage generating circuit, such as an internal supply voltage generating circuit, incorporated in a chip in order to obtain a desired DC voltage for an internal operation of the chip. Typically, the output of such a DC voltage generating circuit is used as a bias voltage for an operation of the memory device. On the other hand, a separate test voltage is also required in a particular mode using a high voltage as in a burn-in test. In order to supply such a test voltage with a high voltage level, a test voltage generating circuit, which is designed differently from the above-mentioned DC voltage generating circuit, should be additionally incorporated in the chip. In other words, the chip should have both the DC voltage generating circuit for the application of a bias voltage and the test voltage generating circuit for a burn-in test operation. As a result, the semiconductor memory device degrades in integration degree. In order to solve this problem, a method has been proposed in which the output voltage of the DC voltage generating circuit, such as the internal supply voltage generating circuit, depends on the external supply voltage. In accordance with this method, the DC voltage generating circuit is controlled to clamp its output voltage to a desired level for the application of a bias voltage in a certain range of the external supply voltage while increasing the output voltage in proportion to the level of the external supply voltage when the external supply voltage is higher than a particular voltage level. In order to achieve such a control, a voltage clamping circuit is employed in semiconductor memory devices. Referring to FIG. 1, the waveform of an output voltage generated from the DC voltage generating circuit under the control of a voltage clamping circuit is best shown. In a particular range of an external supply voltage, for example, a range between voltage levels V1 and V2 in FIG. 1, the output voltage Vout of the DC voltage generating circuit is clamped to a voltage level Vc. On the other hand, the output voltage Vout increases in proportion to a variation in the external supply voltage when the external supply voltage is higher than the voltage level V2. Accordingly, when the level of the external supply voltage applied to the DC voltage generating circuit is in the interval between voltage levels V1 and V2, it supplies a bias voltage to circuits provided in a chip associated therewith. The DC voltage generating circuit also supplies a high-level voltage required for a test operation to the circuits of the chip when the level of the external supply voltage is higher than the voltage level V2.
However, such a voltage clamping circuit carries out a voltage clamping function in a fixed clamping range. In other words, the clamping range of the voltage clamping circuit can not be adjusted. It has often been required to use a voltage clamping circuit in which its clamping range is variable. Such a voltage clamping circuit has been realized in accordance with a fuse option adopted to semiconductor memory devices. Voltage clamping circuits utilizing such a fuse option are illustrated in FIGS. 2 and 3, respectively.
Referring to FIG. 2, four diodes 11 to 14 are connected in series between an external supply voltage terminal EVcc and a node Ni on the output line of a DC voltage generating circuit 10. Fuses 15 to 18 are coupled in parallel to the diodes 11 to 14, respectively. In the circuit shown in FIG. 2, the maximum clamping interval for an output voltage of the DC voltage generating circuit 10 corresponds to the sum of threshold voltages of the diodes 11 to 14. For example, when the threshold voltage of each diode is Vt, the maximum clamping interval, V1-V2, corresponds to 4Vt. Where it is desired to adjust the clamping interval from the maximum interval, some or all of the fuses 15 to 18 are cut. Accordingly, the clamping interval is determined in accordance with the number of cut fuses.
Referring to FIG. 3, four PMOS transistors 21 to 24 are connected in series between an external supply voltage terminal EVcc and a node N2 on the output line of a DC voltage generating circuit 20. Fuses 25 to 28 are coupled in parallel to the PMOS transistors 21 to 24, respectively. In the circuit shown in FIG. 3, the maximum clamping interval for an output voltage of the DC voltage generating circuit 20 corresponds to the sum of threshold voltages of the PMOS transistors 21 to 24. For example, when the threshold voltage of each diode is Vt, the maximum clamping interval, V1-V2, corresponds to 4Vt. Where it is desired to adjust the clamping interval from the maximum interval, some or all of the fuses 25 to 28 are cut in the same manner as in FIG. 2. Accordingly, the clamping interval is determined in accordance with the number of cut fuses, as in the case of FIG. 2.
As mentioned above, the conventional voltage clamping circuits of FIGS. 2 and 3 use fuses for the adjustment of the clamping interval. In other words, the clamping interval of the output voltage is adjusted in accordance with a fuse option. Some or all of the fuses are cut in accordance with the fuse option. Such a fuse option is conducted during fabricating semiconductor memory devices. That is, the fabrication of chips is completed after a number of processing steps, following the cutting of fuses, are conducted. For this reason, semiconductor memory devices having desired clamp intervals can be obtained only after a considerable period of time elapses from the point of time when the demand of the user is accepted. As a result, a variation in market may occur in the interval between the point of time when the demand of the user is accepted and the point of time when the semiconductor memory devices are obtained. Such a variation in market may cause severe damage to the manufacturer of the semiconductor memory devices.